Fix for MSYS/MINGW

This commit is contained in:
SChernykh 2018-09-24 19:31:53 +02:00
parent f4a867b70f
commit 201be4d31b
2 changed files with 11 additions and 0 deletions

View file

@ -12,16 +12,24 @@
ALIGN 16
FN_PREFIX(cnv2_mainloop_ivybridge_asm):
#ifndef XMRIG_WINDOWS
sub rsp, 48
mov rcx, rdi
#endif
#include "cnv2_main_loop_ivybridge.inc"
#ifndef XMRIG_WINDOWS
add rsp, 48
#endif
ret 0
ALIGN 16
FN_PREFIX(cnv2_mainloop_ryzen_asm):
#ifndef XMRIG_WINDOWS
sub rsp, 48
mov rcx, rdi
#endif
#include "cnv2_main_loop_ryzen.inc"
#ifndef XMRIG_WINDOWS
add rsp, 48
#endif
ret 0