Special case for Intel CPUs with 1 MB L2 cache per core.

This commit is contained in:
XMRig 2019-07-26 16:22:44 +07:00
parent ffa6bda106
commit 35d9c755e0
2 changed files with 33 additions and 14 deletions

View file

@ -147,7 +147,7 @@ void xmrig::Rx::initDataset(size_t index, const uint8_t *seed, const Algorithm &
if (!d_ptr->datasets[index]) {
const uint64_t ts = Chrono::steadyMSecs();
LOG_INFO("%s" MAGENTA_BOLD(" allocate") CYAN_BOLD(" %zu MiB") BLACK_BOLD(" (%zu+%zu) for RandomX dataset & cache"),
LOG_INFO("%s" MAGENTA_BOLD(" allocate") CYAN_BOLD(" %zu MB") BLACK_BOLD(" (%zu+%zu) for RandomX dataset & cache"),
tag,
(RxDataset::size() + RxCache::size()) / 1024 / 1024,
RxDataset::size() / 1024 / 1024,