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Merge pull request #3646 from SChernykh/dev

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Optimized autoconfig for AMD CPUs with < 2 MB L3 cache per thread
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xmrig 2025-03-22 18:36:09 +07:00 • committed by GitHub
commit 36fdfa2694
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1 changed files with 7 additions and 2 deletions
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7
src/backend/cpu/platform/HwlocCpuInfo.cpp
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@ -320,11 +320,16 @@ void xmrig::HwlocCpuInfo::processTopLevelCache(hwloc_obj_t cache, const Algorith
L2 += l2->attr->cache.size; L2 += l2->attr->cache.size;
L2_associativity = l2->attr->cache.associativity; L2_associativity = l2->attr->cache.associativity;
if (L3_exclusive && l2->attr->cache.size >= scratchpad) { if (L3_exclusive) {
if (vendor() == VENDOR_AMD) {
extra += std::min<size_t>(l2->attr->cache.size, scratchpad);
}
else if (l2->attr->cache.size >= scratchpad) {
extra += scratchpad; extra += scratchpad;
} }
} }
} }
}
// This code is supposed to run only on Intel CPUs // This code is supposed to run only on Intel CPUs
if ((vendor() == VENDOR_INTEL) && (scratchpad == 2 * oneMiB)) { if ((vendor() == VENDOR_INTEL) && (scratchpad == 2 * oneMiB)) {