Adjust panthera code for MSVC 2019 compilation (fixes #41)
This commit is contained in:
Tony Butler
parent
174663bb50
commit
504f608871
3 changed files with 29 additions and 12 deletions
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@ -37,12 +37,19 @@
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#ifdef __ICC
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/* Miscompile with icc 14.0.0 (at least), so don't use restrict there */
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#define restrict
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#define static_restrict static
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#elif defined(_MSC_VER)
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#define restrict
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#define static_restrict
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#elif __STDC_VERSION__ >= 199901L
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/* Have restrict */
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#define static_restrict static restrict
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#elif defined(__GNUC__)
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#define restrict __restrict
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#define static_restrict static __restrict
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#else
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#define restrict
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#define static_restrict
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#endif
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/*
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@ -132,9 +139,9 @@ static const uint32_t Krnd[64] = {
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* the 512-bit input block to produce a new state.
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*/
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static void
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SHA256_Transform(uint32_t state[static restrict 8],
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const uint8_t block[static restrict 64],
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uint32_t W[static restrict 64], uint32_t S[static restrict 8])
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SHA256_Transform(uint32_t state[static_restrict 8],
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const uint8_t block[static_restrict 64],
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uint32_t W[static_restrict 64], uint32_t S[static_restrict 8])
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{
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int i;
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@ -203,7 +210,7 @@ static const uint8_t PAD[64] = {
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/* Add padding and terminating bit-count. */
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static void
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SHA256_Pad(SHA256_CTX * ctx, uint32_t tmp32[static restrict 72])
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SHA256_Pad(SHA256_CTX * ctx, uint32_t tmp32[static_restrict 72])
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{
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size_t r;
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@ -257,7 +264,7 @@ SHA256_Init(SHA256_CTX * ctx)
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*/
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static void
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_SHA256_Update(SHA256_CTX * ctx, const void * in, size_t len,
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uint32_t tmp32[static restrict 72])
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uint32_t tmp32[static_restrict 72])
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{
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uint32_t r;
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const uint8_t * src = in;
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@ -315,7 +322,7 @@ SHA256_Update(SHA256_CTX * ctx, const void * in, size_t len)
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*/
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static void
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_SHA256_Final(uint8_t digest[32], SHA256_CTX * ctx,
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uint32_t tmp32[static restrict 72])
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uint32_t tmp32[static_restrict 72])
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{
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/* Add padding. */
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@ -367,8 +374,8 @@ SHA256_Buf(const void * in, size_t len, uint8_t digest[32])
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*/
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static void
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_HMAC_SHA256_Init(HMAC_SHA256_CTX * ctx, const void * _K, size_t Klen,
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uint32_t tmp32[static restrict 72], uint8_t pad[static restrict 64],
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uint8_t khash[static restrict 32])
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uint32_t tmp32[static_restrict 72], uint8_t pad[static_restrict 64],
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uint8_t khash[static_restrict 32])
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{
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const uint8_t * K = _K;
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size_t i;
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@ -420,7 +427,7 @@ HMAC_SHA256_Init(HMAC_SHA256_CTX * ctx, const void * _K, size_t Klen)
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*/
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static void
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_HMAC_SHA256_Update(HMAC_SHA256_CTX * ctx, const void * in, size_t len,
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uint32_t tmp32[static restrict 72])
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uint32_t tmp32[static_restrict 72])
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{
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/* Feed data to the inner SHA256 operation. */
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@ -447,7 +454,7 @@ HMAC_SHA256_Update(HMAC_SHA256_CTX * ctx, const void * in, size_t len)
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*/
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static void
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_HMAC_SHA256_Final(uint8_t digest[32], HMAC_SHA256_CTX * ctx,
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uint32_t tmp32[static restrict 72], uint8_t ihash[static restrict 32])
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uint32_t tmp32[static_restrict 72], uint8_t ihash[static_restrict 32])
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{
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/* Finish the inner SHA256 operation. */
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@ -500,8 +507,8 @@ HMAC_SHA256_Buf(const void * K, size_t Klen, const void * in, size_t len,
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/* Add padding and terminating bit-count, but don't invoke Transform yet. */
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static int
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SHA256_Pad_Almost(SHA256_CTX * ctx, uint8_t len[static restrict 8],
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uint32_t tmp32[static restrict 72])
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SHA256_Pad_Almost(SHA256_CTX * ctx, uint8_t len[static_restrict 8],
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uint32_t tmp32[static_restrict 72])
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{
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uint32_t r;
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@ -49,6 +49,7 @@
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* no slowdown from the prefixes is generally observed on AMD CPUs supporting
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* XOP, some slowdown is sometimes observed on Intel CPUs with AVX.
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*/
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#if !defined(_MSC_VER)
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#ifdef __XOP__
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#warning "Note: XOP is enabled. That's great."
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#elif defined(__AVX__)
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@ -60,6 +61,7 @@
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#else
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#warning "Note: building generic code for non-x86. That's OK."
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#endif
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#endif
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/*
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* The SSE4 code version has fewer instructions than the generic SSE2 version,
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@ -102,6 +104,10 @@
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#include "yespower-platform.c"
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#if defined(_MSC_VER)
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#define __thread
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#endif
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#if __STDC_VERSION__ >= 199901L
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/* Have restrict */
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#elif defined(__GNUC__)
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@ -527,7 +533,9 @@ static volatile uint64_t Smask2var = Smask2;
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/* 64-bit without AVX. This relies on out-of-order execution and register
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* renaming. It may actually be fastest on CPUs with AVX(2) as well - e.g.,
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* it runs great on Haswell. */
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#if !defined(_MSC_VER)
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#warning "Note: using x86-64 inline assembly for pwxform. That's great."
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#endif
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#undef MAYBE_MEMORY_BARRIER
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#define MAYBE_MEMORY_BARRIER \
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__asm__("" : : : "memory");
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@ -44,7 +44,9 @@
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* yespower-opt.c.
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*/
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#if !defined(_MSC_VER)
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#warning "This reference implementation is deliberately mostly not optimized. Use yespower-opt.c instead unless you're testing (against) the reference implementation on purpose."
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#endif
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#include <errno.h>
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#include <stdint.h>
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