ARM64 JIT: don't use x18 register
From https://developer.apple.com/documentation/xcode/writing-arm64-code-for-apple-platforms > The platforms reserve register x18. Don’t use this register. This PR fixes invalid hashes when running on Apple silicon with the latest macOS SDK.
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SChernykh
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08901a9a4b
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5e66efabcf
2 changed files with 75 additions and 77 deletions
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@ -72,9 +72,9 @@
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# x15 -> "r7"
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# x16 -> spAddr0
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# x17 -> spAddr1
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# x18 -> temporary
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# x18 -> unused (platform register, don't touch it)
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# x19 -> temporary
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# x20 -> literal for IMUL_RCP
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# x20 -> temporary
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# x21 -> literal for IMUL_RCP
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# x22 -> literal for IMUL_RCP
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# x23 -> literal for IMUL_RCP
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@ -109,7 +109,7 @@ DECL(randomx_program_aarch64):
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# Save callee-saved registers
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sub sp, sp, 192
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stp x16, x17, [sp]
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stp x18, x19, [sp, 16]
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str x19, [sp, 16]
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stp x20, x21, [sp, 32]
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stp x22, x23, [sp, 48]
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stp x24, x25, [sp, 64]
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@ -164,7 +164,6 @@ DECL(randomx_program_aarch64):
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# Read literals
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ldr x0, literal_x0
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ldr x11, literal_x11
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ldr x20, literal_x20
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ldr x21, literal_x21
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ldr x22, literal_x22
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ldr x23, literal_x23
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@ -196,11 +195,11 @@ DECL(randomx_program_aarch64):
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DECL(randomx_program_aarch64_main_loop):
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# spAddr0 = spMix1 & ScratchpadL3Mask64;
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# spAddr1 = (spMix1 >> 32) & ScratchpadL3Mask64;
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lsr x18, x10, 32
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lsr x20, x10, 32
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# Actual mask will be inserted by JIT compiler
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and w16, w10, 1
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and w17, w18, 1
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and w17, w20, 1
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# x16 = scratchpad + spAddr0
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# x17 = scratchpad + spAddr1
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@ -208,31 +207,31 @@ DECL(randomx_program_aarch64_main_loop):
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add x17, x17, x2
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# xor integer registers with scratchpad data (spAddr0)
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ldp x18, x19, [x16]
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eor x4, x4, x18
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ldp x20, x19, [x16]
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eor x4, x4, x20
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eor x5, x5, x19
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ldp x18, x19, [x16, 16]
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eor x6, x6, x18
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ldp x20, x19, [x16, 16]
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eor x6, x6, x20
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eor x7, x7, x19
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ldp x18, x19, [x16, 32]
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eor x12, x12, x18
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ldp x20, x19, [x16, 32]
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eor x12, x12, x20
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eor x13, x13, x19
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ldp x18, x19, [x16, 48]
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eor x14, x14, x18
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ldp x20, x19, [x16, 48]
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eor x14, x14, x20
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eor x15, x15, x19
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# Load group F registers (spAddr1)
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ldpsw x18, x19, [x17]
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ins v16.d[0], x18
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ldpsw x20, x19, [x17]
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ins v16.d[0], x20
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ins v16.d[1], x19
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ldpsw x18, x19, [x17, 8]
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ins v17.d[0], x18
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ldpsw x20, x19, [x17, 8]
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ins v17.d[0], x20
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ins v17.d[1], x19
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ldpsw x18, x19, [x17, 16]
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ins v18.d[0], x18
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ldpsw x20, x19, [x17, 16]
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ins v18.d[0], x20
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ins v18.d[1], x19
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ldpsw x18, x19, [x17, 24]
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ins v19.d[0], x18
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ldpsw x20, x19, [x17, 24]
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ins v19.d[0], x20
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ins v19.d[1], x19
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scvtf v16.2d, v16.2d
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scvtf v17.2d, v17.2d
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@ -240,17 +239,17 @@ DECL(randomx_program_aarch64_main_loop):
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scvtf v19.2d, v19.2d
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# Load group E registers (spAddr1)
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ldpsw x18, x19, [x17, 32]
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ins v20.d[0], x18
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ldpsw x20, x19, [x17, 32]
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ins v20.d[0], x20
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ins v20.d[1], x19
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ldpsw x18, x19, [x17, 40]
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ins v21.d[0], x18
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ldpsw x20, x19, [x17, 40]
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ins v21.d[0], x20
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ins v21.d[1], x19
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ldpsw x18, x19, [x17, 48]
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ins v22.d[0], x18
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ldpsw x20, x19, [x17, 48]
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ins v22.d[0], x20
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ins v22.d[1], x19
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ldpsw x18, x19, [x17, 56]
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ins v23.d[0], x18
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ldpsw x20, x19, [x17, 56]
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ins v23.d[0], x20
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ins v23.d[1], x19
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scvtf v20.2d, v20.2d
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scvtf v21.2d, v21.2d
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@ -273,7 +272,6 @@ DECL(randomx_program_aarch64_vm_instructions):
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literal_x0: .fill 1,8,0
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literal_x11: .fill 1,8,0
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literal_x20: .fill 1,8,0
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literal_x21: .fill 1,8,0
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literal_x22: .fill 1,8,0
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literal_x23: .fill 1,8,0
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@ -309,17 +307,17 @@ DECL(randomx_program_aarch64_vm_instructions_end):
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lsr x10, x9, 32
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# mx ^= r[readReg2] ^ r[readReg3];
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eor x9, x9, x18
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eor x9, x9, x20
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# Calculate dataset pointer for dataset prefetch
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mov w18, w9
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mov w20, w9
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DECL(randomx_program_aarch64_cacheline_align_mask1):
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# Actual mask will be inserted by JIT compiler
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and x18, x18, 1
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add x18, x18, x1
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and x20, x20, 1
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add x20, x20, x1
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# Prefetch dataset data
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prfm pldl2strm, [x18]
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prfm pldl2strm, [x20]
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# mx <-> ma
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ror x9, x9, 32
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@ -331,17 +329,17 @@ DECL(randomx_program_aarch64_cacheline_align_mask2):
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DECL(randomx_program_aarch64_xor_with_dataset_line):
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# xor integer registers with dataset data
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ldp x18, x19, [x10]
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eor x4, x4, x18
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ldp x20, x19, [x10]
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eor x4, x4, x20
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eor x5, x5, x19
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ldp x18, x19, [x10, 16]
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eor x6, x6, x18
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ldp x20, x19, [x10, 16]
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eor x6, x6, x20
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eor x7, x7, x19
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ldp x18, x19, [x10, 32]
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eor x12, x12, x18
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ldp x20, x19, [x10, 32]
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eor x12, x12, x20
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eor x13, x13, x19
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ldp x18, x19, [x10, 48]
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eor x14, x14, x18
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ldp x20, x19, [x10, 48]
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eor x14, x14, x20
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eor x15, x15, x19
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DECL(randomx_program_aarch64_update_spMix1):
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@ -384,7 +382,7 @@ DECL(randomx_program_aarch64_update_spMix1):
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# Restore callee-saved registers
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ldp x16, x17, [sp]
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ldp x18, x19, [sp, 16]
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ldr x19, [sp, 16]
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ldp x20, x21, [sp, 32]
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ldp x22, x23, [sp, 48]
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ldp x24, x25, [sp, 64]
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@ -405,7 +403,7 @@ DECL(randomx_program_aarch64_vm_instructions_end_light):
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stp x2, x30, [sp, 80]
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# mx ^= r[readReg2] ^ r[readReg3];
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eor x9, x9, x18
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eor x9, x9, x20
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# mx <-> ma
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ror x9, x9, 32
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@ -447,8 +445,8 @@ DECL(randomx_program_aarch64_light_dataset_offset):
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# x3 -> end item
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DECL(randomx_init_dataset_aarch64):
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# Save x30 (return address)
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str x30, [sp, -16]!
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# Save x20 (used as temporary, but must be saved to not break ABI) and x30 (return address)
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stp x20, x30, [sp, -16]!
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# Load pointer to cache memory
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ldr x0, [x0]
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@ -460,8 +458,8 @@ DECL(randomx_init_dataset_aarch64_main_loop):
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cmp x2, x3
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bne DECL(randomx_init_dataset_aarch64_main_loop)
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# Restore x30 (return address)
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ldr x30, [sp], 16
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# Restore x20 and x30
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ldp x20, x30, [sp], 16
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ret
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