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MSR preset for Bulldozer CPUs

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Also fixed verbose output for MSR presets with masks.
This commit is contained in:
SChernykh 2020-01-14 19:27:34 +01:00
parent 73722ce186
commit 665e43fecc
6 changed files with 26 additions and 6 deletions
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10
src/crypto/rx/Rx_linux.cpp
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@ -91,13 +91,19 @@ static MsrItem rdmsr(uint32_t reg)
}
static uint64_t get_masked_value(uint64_t old_value, uint64_t new_value, uint64_t mask)
{
return (new_value & mask) | (old_value & ~mask);
}
static bool wrmsr_on_cpu(uint32_t reg, uint32_t cpu, uint64_t value, uint64_t mask)
{
// If a bit in mask is set to 1, use new value, otherwise use old value
if (mask != MsrItem::kNoMask) {
uint64_t old_value;
if (rdmsr_on_cpu(reg, cpu, old_value)) {
value = (value & mask) | (old_value & ~mask);
value = get_masked_value(old_value, value, mask);
}
}
@ -162,7 +168,7 @@ static bool wrmsr(const MsrItems &preset, bool save)
if (save) {
for (const auto &i : preset) {
auto item = rdmsr(i.reg());
LOG_VERBOSE(CLEAR "%s" CYAN_BOLD("0x%08" PRIx32) CYAN(":0x%016" PRIx64) CYAN_BOLD(" -> 0x%016" PRIx64), tag, i.reg(), item.value(), i.value());
LOG_VERBOSE(CLEAR "%s" CYAN_BOLD("0x%08" PRIx32) CYAN(":0x%016" PRIx64) CYAN_BOLD(" -> 0x%016" PRIx64), tag, i.reg(), item.value(), get_masked_value(item.value(), i.value(), i.mask()));
if (item.isValid()) {
savedState.emplace_back(item);