fzorb/REDACTED-rig
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Integration of cnv2 and asm optimizations for cnv1&cnv2 thx to @SChernykh (#185)

Browse source
This commit is contained in:
Ben Gräf 2018-10-16 00:20:27 +02:00 • committed by GitHub
parent fe5f6f0673
commit 89e210ddd7
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
33 changed files with 4957 additions and 862 deletions
Download patch file Download diff file Expand all files Collapse all files

88
src/crypto/asm/cn_main_loop.S Normal file
View file

@ -0,0 +1,88 @@
#define ALIGN .align
.intel_syntax noprefix
#ifdef __APPLE__
# define FN_PREFIX(fn) _ ## fn
.text
#else
# define FN_PREFIX(fn) fn
.section .text
#endif
.global FN_PREFIX(cnv1_mainloop_sandybridge_asm)
.global FN_PREFIX(cnv2_mainloop_ivybridge_asm)
.global FN_PREFIX(cnv2_mainloop_ryzen_asm)
.global FN_PREFIX(cnv2_double_mainloop_sandybridge_asm)
.global FN_PREFIX(cnv1_mainloop_soft_aes_sandybridge_asm)
.global FN_PREFIX(cnv2_mainloop_soft_aes_sandybridge_asm)
#ifdef __APPLE__
ALIGN 16
#else
ALIGN 64
#endif
FN_PREFIX(cnv1_mainloop_sandybridge_asm):
sub rsp, 48
mov rcx, rdi
#include "cnv1_mainloop_sandybridge.inc"
add rsp, 48
ret 0
#ifdef __APPLE__
ALIGN 16
#else
ALIGN 64
#endif
FN_PREFIX(cnv2_mainloop_ivybridge_asm):
sub rsp, 48
mov rcx, rdi
#include "cnv2_main_loop_ivybridge.inc"
add rsp, 48
ret 0
#ifdef __APPLE__
ALIGN 16
#else
ALIGN 64
#endif
FN_PREFIX(cnv2_mainloop_ryzen_asm):
sub rsp, 48
mov rcx, rdi
#include "cnv2_main_loop_ryzen.inc"
add rsp, 48
ret 0
#ifdef __APPLE__
ALIGN 16
#else
ALIGN 64
#endif
FN_PREFIX(cnv2_double_mainloop_sandybridge_asm):
sub rsp, 48
mov rcx, rdi
mov rdx, rsi
#include "cnv2_double_main_loop_sandybridge.inc"
add rsp, 48
ret 0
#ifdef __APPLE__
ALIGN 16
#else
ALIGN 64
#endif
FN_PREFIX(cnv1_mainloop_soft_aes_sandybridge_asm):
sub rsp, 48
mov rcx, rdi
#include "cnv1_mainloop_soft_aes_sandybridge.inc"
add rsp, 48
ret 0
#ifdef __APPLE__
ALIGN 16
#else
ALIGN 64
#endif
FN_PREFIX(cnv2_mainloop_soft_aes_sandybridge_asm):
sub rsp, 48
mov rcx, rdi
#include "cnv2_mainloop_soft_aes_sandybridge.inc"
add rsp, 48
ret 0