Update hwloc for MSVC.
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25 changed files with 875 additions and 329 deletions
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src/3rdparty/hwloc/include/private/misc.h
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src/3rdparty/hwloc/include/private/misc.h
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@ -1,6 +1,6 @@
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/*
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* Copyright © 2009 CNRS
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* Copyright © 2009-2019 Inria. All rights reserved.
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* Copyright © 2009-2024 Inria. All rights reserved.
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* Copyright © 2009-2012 Université Bordeaux
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* Copyright © 2011 Cisco Systems, Inc. All rights reserved.
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* See COPYING in top-level directory.
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@ -573,4 +573,35 @@ typedef SSIZE_T ssize_t;
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# endif
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#endif
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static __inline float
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hwloc__pci_link_speed(unsigned generation, unsigned lanes)
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{
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float lanespeed;
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/*
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* These are single-direction bandwidths only.
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*
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* Gen1 used NRZ with 8/10 encoding.
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* PCIe Gen1 = 2.5GT/s signal-rate per lane x 8/10 = 0.25GB/s data-rate per lane
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* PCIe Gen2 = 5 GT/s signal-rate per lane x 8/10 = 0.5 GB/s data-rate per lane
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* Gen3 switched to NRZ with 128/130 encoding.
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* PCIe Gen3 = 8 GT/s signal-rate per lane x 128/130 = 1 GB/s data-rate per lane
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* PCIe Gen4 = 16 GT/s signal-rate per lane x 128/130 = 2 GB/s data-rate per lane
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* PCIe Gen5 = 32 GT/s signal-rate per lane x 128/130 = 4 GB/s data-rate per lane
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* Gen6 switched to PAM with with 242/256 FLIT (242B payload protected by 8B CRC + 6B FEC).
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* PCIe Gen6 = 64 GT/s signal-rate per lane x 242/256 = 8 GB/s data-rate per lane
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* PCIe Gen7 = 128GT/s signal-rate per lane x 242/256 = 16 GB/s data-rate per lane
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*/
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/* lanespeed in Gbit/s */
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if (generation <= 2)
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lanespeed = 2.5f * generation * 0.8f;
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else if (generation <= 5)
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lanespeed = 8.0f * (1<<(generation-3)) * 128/130;
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else
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lanespeed = 8.0f * (1<<(generation-3)) * 242/256; /* assume Gen8 will be 256 GT/s and so on */
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/* linkspeed in GB/s */
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return lanespeed * lanes / 8;
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}
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#endif /* HWLOC_PRIVATE_MISC_H */
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