From aba1ad8cfc6570b844d57862644bb6e057b532b5 Mon Sep 17 00:00:00 2001
From: SChernykh <15806605+SChernykh@users.noreply.github.com>
Date: Thu, 19 Jun 2025 12:58:31 +0200
Subject: [PATCH] Tweaked autoconfig for AMD CPUs with < 2 MB L3 cache per
 thread, again (hopefully the last time)

---
 src/backend/cpu/platform/HwlocCpuInfo.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/backend/cpu/platform/HwlocCpuInfo.cpp b/src/backend/cpu/platform/HwlocCpuInfo.cpp
index 01b86e22..f796416b 100644
--- a/src/backend/cpu/platform/HwlocCpuInfo.cpp
+++ b/src/backend/cpu/platform/HwlocCpuInfo.cpp
@@ -320,7 +320,8 @@ void xmrig::HwlocCpuInfo::processTopLevelCache(hwloc_obj_t cache, const Algorith
             L2_associativity = l2->attr->cache.associativity;
 
             if (L3_exclusive) {
-                if (vendor() == VENDOR_AMD) {
+                if ((vendor() == VENDOR_AMD) && ((arch() == ARCH_ZEN4) || (arch() == ARCH_ZEN5))) {
+                    // Use extra L2 only on newer CPUs because older CPUs (Zen 3 and older) don't benefit from it.
                     // For some reason, AMD CPUs can use only half of the exclusive L2/L3 cache combo efficiently
                     extra += std::min<size_t>(l2->attr->cache.size / 2, scratchpad);
                 }