XMRigCC 2.0 (#263)

# 2.0.0
**Thx to @xmrig and @SChernykh awesome work!**
* Full Rebase on XMRig 3.1.1 
     * randomX/wow/XL
     * NUMA support
     * flexible multi algorithm configuration
     * unlimited switching between incompatible algorithms at runtime
* Argon2, UPX2 (Nice hashrate improvement) and CN-Conceal support integrated like in previous version
* 5-10% Hashrate improvement on ARMv8 CPUs when mining CN based algos compared to stock xmrig
* Fully compatible to XMRigCCServer 1.9.5 no server upgrade needed!
**New XMRigCCServer will be released soon with new features**

src/3rdparty/argon2/arch/x86_64/lib/argon2-arch.c

@@ -4,6 +4,7 @@
 
 #include "impl-select.h"
 
+#include "cpu-flags.h"
 #include "argon2-sse2.h"
 #include "argon2-ssse3.h"
 #include "argon2-xop.h"
@@ -33,6 +34,8 @@ void argon2_get_impl_list(argon2_impl_list *list)
         { "AVX-512F",   check_avx512f,  fill_segment_avx512f },
     };
 
+    cpu_flags_get();
+
     list->count = sizeof(IMPLS) / sizeof(IMPLS[0]);
     list->entries = IMPLS;
 }

src/3rdparty/argon2/arch/x86_64/lib/argon2-avx2.c

@@ -3,7 +3,13 @@
 #ifdef HAVE_AVX2
 #include <string.h>
 
-#include <immintrin.h>
+#ifdef __GNUC__
+#   include <x86intrin.h>
+#else
+#   include <intrin.h>
+#endif
+
+#include "cpu-flags.h"
 
 #define r16 (_mm256_setr_epi8( \
      2,  3,  4,  5,  6,  7,  0,  1, \
@@ -323,7 +329,7 @@ void fill_segment_avx2(const argon2_instance_t *instance,
 
 int check_avx2(void)
 {
-    return 1;
+    return cpu_flags_have_avx2();
 }
 
 #else

src/3rdparty/argon2/arch/x86_64/lib/argon2-avx512f.c

@@ -4,7 +4,13 @@
 #include <stdint.h>
 #include <string.h>
 
-#include <immintrin.h>
+#ifdef __GNUC__
+#   include <x86intrin.h>
+#else
+#   include <intrin.h>
+#endif
+
+#include "cpu-flags.h"
 
 #define ror64(x, n) _mm512_ror_epi64((x), (n))
 
@@ -308,7 +314,7 @@ void fill_segment_avx512f(const argon2_instance_t *instance,
 
 int check_avx512f(void)
 {
-    return 1;
+    return cpu_flags_have_avx512f();
 }
 
 #else

src/3rdparty/argon2/arch/x86_64/lib/argon2-sse2.c

@@ -1,7 +1,13 @@
 #include "argon2-sse2.h"
 
 #ifdef HAVE_SSE2
-#include <immintrin.h>
+#ifdef __GNUC__
+#   include <x86intrin.h>
+#else
+#   include <intrin.h>
+#endif
+
+#include "cpu-flags.h"
 
 #define ror64_16(x) \
     _mm_shufflehi_epi16( \
@@ -104,7 +110,7 @@ void fill_segment_sse2(const argon2_instance_t *instance,
 
 int check_sse2(void)
 {
-    return 1;
+    return cpu_flags_have_sse2();
 }
 
 #else

src/3rdparty/argon2/arch/x86_64/lib/argon2-ssse3.c

@@ -3,7 +3,13 @@
 #ifdef HAVE_SSSE3
 #include <string.h>
 
-#include <immintrin.h>
+#ifdef __GNUC__
+#   include <x86intrin.h>
+#else
+#   include <intrin.h>
+#endif
+
+#include "cpu-flags.h"
 
 #define r16 (_mm_setr_epi8( \
      2,  3,  4,  5,  6,  7,  0,  1, \
@@ -116,7 +122,7 @@ void fill_segment_ssse3(const argon2_instance_t *instance,
 
 int check_ssse3(void)
 {
-    return 1;
+    return cpu_flags_have_ssse3();
 }
 
 #else

src/3rdparty/argon2/arch/x86_64/lib/argon2-template-128.h

@@ -1,6 +1,10 @@
 #include <string.h>
 
-#include <immintrin.h>
+#ifdef __GNUC__
+#   include <x86intrin.h>
+#else
+#   include <intrin.h>
+#endif
 
 #include "core.h"
 

src/3rdparty/argon2/arch/x86_64/lib/argon2-xop.c

@@ -3,7 +3,13 @@
 #ifdef HAVE_XOP
 #include <string.h>
 
-#include <immintrin.h>
+#ifdef __GNUC__
+#   include <x86intrin.h>
+#else
+#   include <intrin.h>
+#endif
+
+#include "cpu-flags.h"
 
 #define ror64(x, c) _mm_roti_epi64((x), -(c))
 
@@ -104,7 +110,7 @@ void fill_segment_xop(const argon2_instance_t *instance,
 
 int check_xop(void)
 {
-    return 1;
+    return cpu_flags_have_xop();
 }
 
 #else

src/3rdparty/argon2/arch/x86_64/lib/cpu-flags.c

@@ -0,0 +1,129 @@
+#include <stdbool.h>
+#include <stdint.h>
+
+
+#include "cpu-flags.h"
+
+#include <stdio.h>
+
+#ifdef _MSC_VER
+#   include <intrin.h>
+#else
+#   include <cpuid.h>
+#endif
+
+#ifndef bit_OSXSAVE
+#   define bit_OSXSAVE (1 << 27)
+#endif
+
+#ifndef bit_SSE2
+#   define bit_SSE2 (1 << 26)
+#endif
+
+#ifndef bit_SSSE3
+#   define bit_SSSE3 (1 << 9)
+#endif
+
+#ifndef bit_AVX2
+#   define bit_AVX2 (1 << 5)
+#endif
+
+#ifndef bit_AVX512F
+#   define bit_AVX512F (1 << 16)
+#endif
+
+#ifndef bit_XOP
+#   define bit_XOP (1 << 11)
+#endif
+
+#define PROCESSOR_INFO    (1)
+#define EXTENDED_FEATURES (7)
+
+#define EAX_Reg  (0)
+#define EBX_Reg  (1)
+#define ECX_Reg  (2)
+#define EDX_Reg  (3)
+
+
+enum {
+    X86_64_FEATURE_SSE2     = (1 << 0),
+    X86_64_FEATURE_SSSE3    = (1 << 1),
+    X86_64_FEATURE_XOP      = (1 << 2),
+    X86_64_FEATURE_AVX2     = (1 << 3),
+    X86_64_FEATURE_AVX512F  = (1 << 4),
+};
+
+static unsigned int cpu_flags;
+
+
+static inline void cpuid(uint32_t level, int32_t output[4])
+{
+#   ifdef _MSC_VER
+    __cpuid(output, (int) level);
+#   else
+    __cpuid_count(level, 0, output[0], output[1], output[2], output[3]);
+#   endif
+}
+
+
+static bool has_feature(uint32_t level, uint32_t reg, int32_t bit)
+{
+    int32_t cpu_info[4] = { 0 };
+    cpuid(level, cpu_info);
+
+    return (cpu_info[reg] & bit) != 0;
+}
+
+
+void cpu_flags_get(void)
+{
+    if (has_feature(PROCESSOR_INFO, EDX_Reg, bit_SSE2)) {
+        cpu_flags |= X86_64_FEATURE_SSE2;
+    }
+
+    if (has_feature(PROCESSOR_INFO, ECX_Reg, bit_SSSE3)) {
+        cpu_flags |= X86_64_FEATURE_SSSE3;
+    }
+
+    if (!has_feature(PROCESSOR_INFO, ECX_Reg, bit_OSXSAVE)) {
+        return;
+    }
+
+    if (has_feature(EXTENDED_FEATURES, EBX_Reg, bit_AVX2)) {
+        cpu_flags |= X86_64_FEATURE_AVX2;
+    }
+
+    if (has_feature(EXTENDED_FEATURES, EBX_Reg, bit_AVX512F)) {
+        cpu_flags |= X86_64_FEATURE_AVX512F;
+    }
+
+    if (has_feature(0x80000001, ECX_Reg, bit_XOP)) {
+        cpu_flags |= X86_64_FEATURE_XOP;
+    }
+}
+
+int cpu_flags_have_sse2(void)
+{
+    return cpu_flags & X86_64_FEATURE_SSE2;
+}
+
+int cpu_flags_have_ssse3(void)
+{
+    return cpu_flags & X86_64_FEATURE_SSSE3;
+}
+
+int cpu_flags_have_xop(void)
+{
+    return cpu_flags & X86_64_FEATURE_XOP;
+}
+
+int cpu_flags_have_avx2(void)
+{
+    return cpu_flags & X86_64_FEATURE_AVX2;
+}
+
+int cpu_flags_have_avx512f(void)
+{
+    return cpu_flags & X86_64_FEATURE_AVX512F;
+}
+

src/3rdparty/argon2/arch/x86_64/lib/cpu-flags.h

@@ -0,0 +1,12 @@
+#ifndef ARGON2_CPU_FLAGS_H
+#define ARGON2_CPU_FLAGS_H
+
+void cpu_flags_get(void);
+
+int cpu_flags_have_sse2(void);
+int cpu_flags_have_ssse3(void);
+int cpu_flags_have_xop(void);
+int cpu_flags_have_avx2(void);
+int cpu_flags_have_avx512f(void);
+
+#endif // ARGON2_CPU_FLAGS_H

src/3rdparty/argon2/arch/x86_64/src/test-feature-avx2.c

@@ -0,0 +1,8 @@
+#include <x86intrin.h>
+
+void function_avx2(__m256i *dst, const __m256i *a, const __m256i *b)
+{
+    *dst = _mm256_xor_si256(*a, *b);
+}
+
+int main(void) { return 0; }

src/3rdparty/argon2/arch/x86_64/src/test-feature-avx512f.c

@@ -0,0 +1,8 @@
+#include <x86intrin.h>
+
+void function_avx512f(__m512i *dst, const __m512i *a)
+{
+    *dst = _mm512_ror_epi64(*a, 57);
+}
+
+int main(void) { return 0; }

src/3rdparty/argon2/arch/x86_64/src/test-feature-sse2.c

@@ -0,0 +1,8 @@
+#include <x86intrin.h>
+
+void function_sse2(__m128i *dst, const __m128i *a, const __m128i *b)
+{
+    *dst = _mm_xor_si128(*a, *b);
+}
+
+int main(void) { return 0; }

src/3rdparty/argon2/arch/x86_64/src/test-feature-ssse3.c

@@ -0,0 +1,8 @@
+#include <x86intrin.h>
+
+void function_ssse3(__m128i *dst, const __m128i *a, const __m128i *b)
+{
+    *dst = _mm_shuffle_epi8(*a, *b);
+}
+
+int main(void) { return 0; }

src/3rdparty/argon2/arch/x86_64/src/test-feature-xop.c

@@ -0,0 +1,8 @@
+#include <x86intrin.h>
+
+void function_xop(__m128i *dst, const __m128i *a, int b)
+{
+    *dst = _mm_roti_epi64(*a, b);
+}
+
+int main(void) { return 0; }