RandomX: added cache QoS support
False by default. If set to true, all non-mining CPU cores will not have access to L3 cache.
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e5a2689052
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c83429c55c
10 changed files with 126 additions and 19 deletions
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@ -30,6 +30,7 @@
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#include "crypto/rx/Rx.h"
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#include "backend/cpu/Cpu.h"
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#include "backend/cpu/CpuThread.h"
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#include "base/io/log/Log.h"
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#include "base/kernel/Platform.h"
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#include "base/tools/Chrono.h"
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@ -256,7 +257,7 @@ static bool wrmsr(HANDLE driver, uint32_t reg, uint64_t value, uint64_t mask)
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}
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static bool wrmsr(const MsrItems &preset, bool save)
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static bool wrmsr(const MsrItems &preset, const std::vector<CpuThread>& threads, bool cache_qos, bool save)
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{
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bool success = true;
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@ -282,14 +283,52 @@ static bool wrmsr(const MsrItems &preset, bool save)
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}
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}
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std::thread wrmsr_thread([driver, &preset, &success]() {
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for (uint32_t i = 0, n = Cpu::info()->threads(); i < n; ++i) {
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const uint32_t n = Cpu::info()->threads();
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// Which CPU cores will have access to the full L3 cache
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std::vector<bool> cacheEnabled(n, false);
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bool cacheQoSDisabled = threads.empty();
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for (const CpuThread& t : threads) {
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// If some thread has no affinity or wrong affinity, disable cache QoS
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if ((t.affinity() < 0) || (t.affinity() >= n)) {
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cacheQoSDisabled = true;
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if (cache_qos) {
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LOG_WARN(CLEAR "%s" YELLOW_BOLD_S "Cache QoS can only be enabled when all mining threads have affinity set", tag);
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}
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break;
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}
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cacheEnabled[t.affinity()] = true;
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}
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if (cache_qos && !Cpu::info()->hasCatL3()) {
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LOG_WARN(CLEAR "%s" YELLOW_BOLD_S "This CPU doesn't support cat_l3, cache QoS is unavailable", tag);
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cache_qos = false;
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}
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std::thread wrmsr_thread([n, driver, &preset, &cacheEnabled, cache_qos, cacheQoSDisabled, &success]() {
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for (uint32_t i = 0; i < n; ++i) {
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if (!Platform::setThreadAffinity(i)) {
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continue;
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}
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for (const auto &i : preset) {
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success = wrmsr(driver, i.reg(), i.value(), i.mask());
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success &= wrmsr(driver, i.reg(), i.value(), i.mask());
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}
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if (cache_qos) {
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if (cacheQoSDisabled || cacheEnabled[i]) {
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// Assign Class Of Service 0 to current CPU core (default, full L3 cache available)
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success &= wrmsr(driver, 0xC8F, 0, MsrItem::kNoMask);
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}
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else {
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// Disable L3 cache for Class Of Service 1
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success &= wrmsr(driver, 0xC91, 0, MsrItem::kNoMask);
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// Assign Class Of Service 1 to current CPU core
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success &= wrmsr(driver, 0xC8F, 1ULL << 32, MsrItem::kNoMask);
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}
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}
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if (!success) {
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@ -349,7 +388,7 @@ void Rx::setMainLoopBounds(const std::pair<const void*, const void*>& bounds)
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} // namespace xmrig
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void xmrig::Rx::msrInit(const RxConfig &config)
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void xmrig::Rx::msrInit(const RxConfig &config, const std::vector<CpuThread>& threads)
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{
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const auto &preset = config.msrPreset();
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if (preset.empty()) {
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@ -358,7 +397,7 @@ void xmrig::Rx::msrInit(const RxConfig &config)
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const uint64_t ts = Chrono::steadyMSecs();
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if (wrmsr(preset, config.rdmsr())) {
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if (wrmsr(preset, threads, config.cacheQoS(), config.rdmsr())) {
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LOG_NOTICE(CLEAR "%s" GREEN_BOLD_S "register values for \"%s\" preset has been set successfully" BLACK_BOLD(" (%" PRIu64 " ms)"), tag, config.msrPresetName(), Chrono::steadyMSecs() - ts);
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}
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else {
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@ -375,7 +414,7 @@ void xmrig::Rx::msrDestroy()
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const uint64_t ts = Chrono::steadyMSecs();
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if (!wrmsr(savedState, false)) {
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if (!wrmsr(savedState, std::vector<CpuThread>(), true, false)) {
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LOG_ERR(CLEAR "%s" RED_BOLD_S "failed to restore initial state" BLACK_BOLD(" (%" PRIu64 " ms)"), tag, Chrono::steadyMSecs() - ts);
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}
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}
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