From e4c30eb0dd9c5b6d3f2af02289d00081c66aba00 Mon Sep 17 00:00:00 2001
From: SChernykh <15806605+SChernykh@users.noreply.github.com>
Date: Wed, 11 Jun 2025 18:34:50 +0200
Subject: [PATCH] Tweaked autoconfig for AMD CPUs with < 2 MB L3 cache per
 thread

---
 src/backend/cpu/platform/HwlocCpuInfo.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/backend/cpu/platform/HwlocCpuInfo.cpp b/src/backend/cpu/platform/HwlocCpuInfo.cpp
index 38fb0a26..40e05a17 100644
--- a/src/backend/cpu/platform/HwlocCpuInfo.cpp
+++ b/src/backend/cpu/platform/HwlocCpuInfo.cpp
@@ -322,7 +322,8 @@ void xmrig::HwlocCpuInfo::processTopLevelCache(hwloc_obj_t cache, const Algorith
 
             if (L3_exclusive) {
                 if (vendor() == VENDOR_AMD) {
-                    extra += std::min<size_t>(l2->attr->cache.size, scratchpad);
+                    // For some reason, AMD CPUs can use only half of the exclusive L2/L3 cache combo efficiently
+                    extra += std::min<size_t>(l2->attr->cache.size / 2, scratchpad);
                 }
                 else if (l2->attr->cache.size >= scratchpad) {
                     extra += scratchpad;