RandomXHFPI
This commit is contained in:
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13 changed files with 190 additions and 7 deletions
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@ -60,6 +60,7 @@ function rx()
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'randomx_constants_wow.h',
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'randomx_constants_wow.h',
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'randomx_constants_loki.h',
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'randomx_constants_loki.h',
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'randomx_constants_arqma.h',
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'randomx_constants_arqma.h',
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'randomx_constants_klaro.h',
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'aes.cl',
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'aes.cl',
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'blake2b.cl',
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'blake2b.cl',
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'randomx_vm.cl',
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'randomx_vm.cl',
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@ -25,6 +25,7 @@
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#define ALGO_AR2_CHUKWA 24
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#define ALGO_AR2_CHUKWA 24
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#define ALGO_AR2_WRKZ 25
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#define ALGO_AR2_WRKZ 25
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#define FAMILY_UNKNOWN 0
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#define FAMILY_UNKNOWN 0
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#define FAMILY_CN 1
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#define FAMILY_CN 1
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#define FAMILY_CN_LITE 2
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#define FAMILY_CN_LITE 2
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97
src/backend/opencl/cl/rx/randomx_constants_klaro.h
Normal file
97
src/backend/opencl/cl/rx/randomx_constants_klaro.h
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@ -0,0 +1,97 @@
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/*
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Copyright (c) 2019 SChernykh
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This file is part of RandomX OpenCL.
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RandomX OpenCL is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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RandomX OpenCL is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with RandomX OpenCL. If not, see <http://www.gnu.org/licenses/>.
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*/
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//Dataset base size in bytes. Must be a power of 2.
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#define RANDOMX_DATASET_BASE_SIZE 2147483648
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//Dataset extra size. Must be divisible by 64.
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#define RANDOMX_DATASET_EXTRA_SIZE 33554368
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//Scratchpad L3 size in bytes. Must be a power of 2.
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#define RANDOMX_SCRATCHPAD_L3 2097152
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//Scratchpad L2 size in bytes. Must be a power of two and less than or equal to RANDOMX_SCRATCHPAD_L3.
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#define RANDOMX_SCRATCHPAD_L2 262144
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//Scratchpad L1 size in bytes. Must be a power of two (minimum 64) and less than or equal to RANDOMX_SCRATCHPAD_L2.
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#define RANDOMX_SCRATCHPAD_L1 16384
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//Jump condition mask size in bits.
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#define RANDOMX_JUMP_BITS 8
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//Jump condition mask offset in bits. The sum of RANDOMX_JUMP_BITS and RANDOMX_JUMP_OFFSET must not exceed 16.
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#define RANDOMX_JUMP_OFFSET 8
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//Integer instructions
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#define RANDOMX_FREQ_IADD_RS 15
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#define RANDOMX_FREQ_IADD_M 2
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#define RANDOMX_FREQ_ISUB_R 16
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#define RANDOMX_FREQ_ISUB_M 2
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#define RANDOMX_FREQ_IMUL_R 16
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#define RANDOMX_FREQ_IMUL_M 4
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#define RANDOMX_FREQ_IMULH_R 4
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#define RANDOMX_FREQ_IMULH_M 1
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#define RANDOMX_FREQ_ISMULH_R 4
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#define RANDOMX_FREQ_ISMULH_M 1
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#define RANDOMX_FREQ_IMUL_RCP 8
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#define RANDOMX_FREQ_INEG_R 2
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#define RANDOMX_FREQ_IXOR_R 5
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#define RANDOMX_FREQ_IXOR_M 2
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#define RANDOMX_FREQ_IROR_R 2
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#define RANDOMX_FREQ_IROL_R 2
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#define RANDOMX_FREQ_ISWAP_R 4
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//Floating point instructions
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#define RANDOMX_FREQ_FSWAP_R 4
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#define RANDOMX_FREQ_FADD_R 20
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#define RANDOMX_FREQ_FADD_M 10
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#define RANDOMX_FREQ_FSUB_R 20
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#define RANDOMX_FREQ_FSUB_M 10
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#define RANDOMX_FREQ_FSCAL_R 6
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#define RANDOMX_FREQ_FMUL_R 20
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#define RANDOMX_FREQ_FMUL2I_R 20
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#define RANDOMX_FREQ_FDIV_M 7
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#define RANDOMX_FREQ_FSQRT_R 16
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//Control instructions
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#define RANDOMX_FREQ_CBRANCH 16
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#define RANDOMX_FREQ_CFROUND 1
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//Store instruction
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#define RANDOMX_FREQ_ISTORE 16
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//No-op instruction
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#define RANDOMX_FREQ_NOP 0
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#define RANDOMX_DATASET_ITEM_SIZE 64
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#define RANDOMX_PROGRAM_SIZE 256
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#define HASH_SIZE 32
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#define ENTROPY_SIZE (128 + RANDOMX_PROGRAM_SIZE * 8)
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#define REGISTERS_SIZE 256
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#define IMM_BUF_SIZE (RANDOMX_PROGRAM_SIZE * 4 - REGISTERS_SIZE)
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#define IMM_INDEX_COUNT ((IMM_BUF_SIZE / 4) - 2)
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#define VM_STATE_SIZE (REGISTERS_SIZE + IMM_BUF_SIZE + RANDOMX_PROGRAM_SIZE * 4)
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#define ROUNDING_MODE (RANDOMX_FREQ_CFROUND ? -1 : 0)
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// Scratchpad L1/L2/L3 bits
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#define LOC_L1 (32 - 14)
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#define LOC_L2 (32 - 18)
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#define LOC_L3 (32 - 21)
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@ -118,6 +118,8 @@ static AlgoName const algorithm_names[] = {
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{ "RandomARQ", nullptr, Algorithm::RX_ARQ },
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{ "RandomARQ", nullptr, Algorithm::RX_ARQ },
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{ "randomx/sfx", "rx/sfx", Algorithm::RX_SFX },
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{ "randomx/sfx", "rx/sfx", Algorithm::RX_SFX },
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{ "RandomSFX", nullptr, Algorithm::RX_SFX },
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{ "RandomSFX", nullptr, Algorithm::RX_SFX },
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{ "randomx/klr", "rx/klaro", Algorithm::RX_KLARO },
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{ "RandomXHFPI", nullptr, Algorithm::RX_KLARO },
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# endif
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# endif
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# ifdef XMRIG_ALGO_ARGON2
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# ifdef XMRIG_ALGO_ARGON2
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{ "argon2/chukwa", nullptr, Algorithm::AR2_CHUKWA },
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{ "argon2/chukwa", nullptr, Algorithm::AR2_CHUKWA },
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@ -69,6 +69,7 @@ public:
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RX_LOKI, // "rx/loki" RandomXL (Loki).
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RX_LOKI, // "rx/loki" RandomXL (Loki).
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RX_ARQ, // "rx/arq" RandomARQ (Arqma).
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RX_ARQ, // "rx/arq" RandomARQ (Arqma).
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RX_SFX, // "rx/sfx" RandomSFX (Safex Cash).
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RX_SFX, // "rx/sfx" RandomSFX (Safex Cash).
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RX_KLARO, // "rx/klaro" RandomHFPI (Klaro Electronic Money).
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AR2_CHUKWA, // "argon2/chukwa" Argon2id (Chukwa).
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AR2_CHUKWA, // "argon2/chukwa" Argon2id (Chukwa).
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AR2_WRKZ, // "argon2/wrkz" Argon2id (WRKZ)
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AR2_WRKZ, // "argon2/wrkz" Argon2id (WRKZ)
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MAX
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MAX
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@ -63,6 +63,7 @@ namespace randomx {
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INSTR_CASE(FSUB_M)
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INSTR_CASE(FSUB_M)
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INSTR_CASE(FSCAL_R)
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INSTR_CASE(FSCAL_R)
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INSTR_CASE(FMUL_R)
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INSTR_CASE(FMUL_R)
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INSTR_CASE(FMUL2I_R)
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INSTR_CASE(FDIV_M)
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INSTR_CASE(FDIV_M)
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INSTR_CASE(FSQRT_R)
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INSTR_CASE(FSQRT_R)
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INSTR_CASE(CBRANCH)
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INSTR_CASE(CBRANCH)
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@ -414,6 +415,17 @@ namespace randomx {
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return;
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return;
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}
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}
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if (opcode < RandomX_CurrentConfig.CEIL_FMUL2I_R) {
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auto dst = instr.dst % RegisterCountFlt;
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int reg_a = (instr.getImm32() & 0xff) % RegistersCount;
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int reg_b = (instr.getImm32()>>8 & 0xff) % RegistersCount;
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ibc.type = InstructionType::FMUL2I_R;
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ibc.fdst = &nreg->e[dst];
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ibc.isrc = &nreg->r[reg_a];
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ibc.isrc2 = &nreg->r[reg_b];
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return;
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}
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if (opcode < RandomX_CurrentConfig.CEIL_FDIV_M) {
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if (opcode < RandomX_CurrentConfig.CEIL_FDIV_M) {
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auto dst = instr.dst % RegisterCountFlt;
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auto dst = instr.dst % RegisterCountFlt;
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auto src = instr.src % RegistersCount;
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auto src = instr.src % RegistersCount;
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@ -52,6 +52,7 @@ namespace randomx {
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const int_reg_t* isrc;
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const int_reg_t* isrc;
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const rx_vec_f128* fsrc;
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const rx_vec_f128* fsrc;
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};
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};
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const int_reg_t* isrc2;
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union {
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union {
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uint64_t imm;
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uint64_t imm;
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int64_t simm;
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int64_t simm;
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@ -205,6 +206,14 @@ namespace randomx {
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*ibc.fdst = rx_mul_vec_f128(*ibc.fdst, *ibc.fsrc);
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*ibc.fdst = rx_mul_vec_f128(*ibc.fdst, *ibc.fsrc);
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}
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}
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static void exe_FMUL2I_R(RANDOMX_EXE_ARGS) {
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const rx_vec_f128 a = _mm_cvtepi32_pd(_mm_set_epi64x(0, *ibc.isrc));
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*ibc.fdst = rx_mul_vec_f128(*ibc.fdst, a);
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const rx_vec_f128 b = _mm_cvtepi32_pd(_mm_set_epi64x(0, *ibc.isrc2));
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*ibc.fdst = rx_mul_vec_f128(*ibc.fdst, b);
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*ibc.fdst = rx_sqrt_vec_f128(*ibc.fdst);
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}
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static void exe_FDIV_M(RANDOMX_EXE_ARGS) {
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static void exe_FDIV_M(RANDOMX_EXE_ARGS) {
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rx_vec_f128 fsrc = maskRegisterExponentMantissa(
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rx_vec_f128 fsrc = maskRegisterExponentMantissa(
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config,
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config,
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void gen_FSUB_M(RANDOMX_GEN_ARGS);
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void gen_FSUB_M(RANDOMX_GEN_ARGS);
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void gen_FSCAL_R(RANDOMX_GEN_ARGS);
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void gen_FSCAL_R(RANDOMX_GEN_ARGS);
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void gen_FMUL_R(RANDOMX_GEN_ARGS);
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void gen_FMUL_R(RANDOMX_GEN_ARGS);
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void gen_FMUL2I_R(RANDOMX_GEN_ARGS);
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void gen_FDIV_M(RANDOMX_GEN_ARGS);
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void gen_FDIV_M(RANDOMX_GEN_ARGS);
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void gen_FSQRT_R(RANDOMX_GEN_ARGS);
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void gen_FSQRT_R(RANDOMX_GEN_ARGS);
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void gen_CBRANCH(RANDOMX_GEN_ARGS);
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void gen_CBRANCH(RANDOMX_GEN_ARGS);
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FSUB_M = 21,
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FSUB_M = 21,
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FSCAL_R = 22,
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FSCAL_R = 22,
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FMUL_R = 23,
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FMUL_R = 23,
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FDIV_M = 24,
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FMUL2I_R = 24,
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FSQRT_R = 25,
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FDIV_M = 25,
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CBRANCH = 26,
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FSQRT_R = 26,
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CFROUND = 27,
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CBRANCH = 27,
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ISTORE = 28,
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CFROUND = 28,
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NOP = 29,
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ISTORE = 29,
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NOP = 30,
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};
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};
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class Instruction {
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class Instruction {
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@ -1038,6 +1038,33 @@ namespace randomx {
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codePos = pos;
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codePos = pos;
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}
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}
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static const uint8_t MOVQ_XMM12_REX[] = { 0x66, 0x4d, 0x0f, 0x6e };
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static const uint8_t CVTDQ2PD_XMM12[] = { 0xf3, 0x45, 0x0f, 0xe6, 0xe4 };
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static const uint8_t MULPD_XMM12[] = { 0x66, 0x41, 0x0f, 0x59 };
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void JitCompilerX86::h_FMUL2I_R(const Instruction& instr) {
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uint8_t* const p = code;
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int pos = codePos;
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const uint32_t dst = instr.dst % RegisterCountFlt;
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int reg_a = (instr.getImm32() & 0xff) % RegistersCount;
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int reg_b = (instr.getImm32()>>8 & 0xff) % RegistersCount;
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emit(MOVQ_XMM12_REX, p, pos);
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emitByte(0xe0 + reg_a, p, pos);
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emit(CVTDQ2PD_XMM12, p, pos);
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emit(MULPD_XMM12, p, pos);
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emitByte(0xc4 + 8 * (dst+4), p, pos);
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emit(MOVQ_XMM12_REX, p, pos);
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emitByte(0xe0 + reg_b, p, pos);
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emit(CVTDQ2PD_XMM12, p, pos);
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emit(MULPD_XMM12, p, pos);
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emitByte(0xc4 + 8 * (dst+4), p, pos);
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emit(SQRTPD, p, pos);
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emitByte(0xe4 + 9 * dst, p, pos);
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codePos = pos;
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}
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void JitCompilerX86::h_FDIV_M(const Instruction& instr) {
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void JitCompilerX86::h_FDIV_M(const Instruction& instr) {
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uint8_t* const p = code;
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uint8_t* const p = code;
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int pos = codePos;
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int pos = codePos;
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void h_FSUB_M(const Instruction&);
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void h_FSUB_M(const Instruction&);
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void h_FSCAL_R(const Instruction&);
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void h_FSCAL_R(const Instruction&);
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void h_FMUL_R(const Instruction&);
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void h_FMUL_R(const Instruction&);
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void h_FMUL2I_R(const Instruction&);
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void h_FDIV_M(const Instruction&);
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void h_FDIV_M(const Instruction&);
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void h_FSQRT_R(const Instruction&);
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void h_FSQRT_R(const Instruction&);
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void h_CBRANCH(const Instruction&);
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void h_CBRANCH(const Instruction&);
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@ -99,6 +99,27 @@ RandomX_ConfigurationSafex::RandomX_ConfigurationSafex()
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ArgonSalt = "RandomSFX\x01";
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ArgonSalt = "RandomSFX\x01";
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}
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}
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RandomX_ConfigurationKlaro::RandomX_ConfigurationKlaro()
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{
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RANDOMX_FREQ_IADD_RS = 15;
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RANDOMX_FREQ_IADD_M = 2;
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RANDOMX_FREQ_ISUB_M = 2;
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RANDOMX_FREQ_IXOR_R = 5;
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RANDOMX_FREQ_IXOR_M = 2;
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RANDOMX_FREQ_IROR_R = 2;
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RANDOMX_FREQ_FADD_R = 20;
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RANDOMX_FREQ_FADD_M = 10;
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RANDOMX_FREQ_FSUB_R = 20;
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RANDOMX_FREQ_FSUB_M = 10;
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RANDOMX_FREQ_FMUL_R = 20;
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RANDOMX_FREQ_FMUL2I_R = 20;
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RANDOMX_FREQ_FDIV_M = 7;
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RANDOMX_FREQ_FSQRT_R = 16;
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RANDOMX_FREQ_CBRANCH = 16;
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}
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RandomX_ConfigurationBase::RandomX_ConfigurationBase()
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RandomX_ConfigurationBase::RandomX_ConfigurationBase()
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: ArgonMemory(262144)
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: ArgonMemory(262144)
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, ArgonIterations(3)
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, ArgonIterations(3)
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@ -276,7 +297,8 @@ void RandomX_ConfigurationBase::Apply()
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INST_HANDLE(FSUB_M, FSUB_R);
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INST_HANDLE(FSUB_M, FSUB_R);
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INST_HANDLE(FSCAL_R, FSUB_M);
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INST_HANDLE(FSCAL_R, FSUB_M);
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INST_HANDLE(FMUL_R, FSCAL_R);
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INST_HANDLE(FMUL_R, FSCAL_R);
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INST_HANDLE(FDIV_M, FMUL_R);
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INST_HANDLE(FMUL2I_R, FMUL_R);
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INST_HANDLE(FDIV_M, FMUL2I_R);
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INST_HANDLE(FSQRT_R, FDIV_M);
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INST_HANDLE(FSQRT_R, FDIV_M);
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INST_HANDLE(CBRANCH, FSQRT_R);
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INST_HANDLE(CBRANCH, FSQRT_R);
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INST_HANDLE(CFROUND, CBRANCH);
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INST_HANDLE(CFROUND, CBRANCH);
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@ -290,6 +312,7 @@ RandomX_ConfigurationWownero RandomX_WowneroConfig;
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RandomX_ConfigurationLoki RandomX_LokiConfig;
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RandomX_ConfigurationLoki RandomX_LokiConfig;
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RandomX_ConfigurationArqma RandomX_ArqmaConfig;
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RandomX_ConfigurationArqma RandomX_ArqmaConfig;
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RandomX_ConfigurationSafex RandomX_SafexConfig;
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RandomX_ConfigurationSafex RandomX_SafexConfig;
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RandomX_ConfigurationKlaro RandomX_KlaroConfig;
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||||||
|
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RandomX_ConfigurationBase RandomX_CurrentConfig;
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RandomX_ConfigurationBase RandomX_CurrentConfig;
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|
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@ -109,6 +109,7 @@ struct RandomX_ConfigurationBase
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uint32_t RANDOMX_FREQ_FSUB_M;
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uint32_t RANDOMX_FREQ_FSUB_M;
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uint32_t RANDOMX_FREQ_FSCAL_R;
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uint32_t RANDOMX_FREQ_FSCAL_R;
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uint32_t RANDOMX_FREQ_FMUL_R;
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uint32_t RANDOMX_FREQ_FMUL_R;
|
||||||
|
uint32_t RANDOMX_FREQ_FMUL2I_R;
|
||||||
uint32_t RANDOMX_FREQ_FDIV_M;
|
uint32_t RANDOMX_FREQ_FDIV_M;
|
||||||
uint32_t RANDOMX_FREQ_FSQRT_R;
|
uint32_t RANDOMX_FREQ_FSQRT_R;
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uint32_t RANDOMX_FREQ_CBRANCH;
|
uint32_t RANDOMX_FREQ_CBRANCH;
|
||||||
|
@ -170,6 +171,7 @@ struct RandomX_ConfigurationBase
|
||||||
int CEIL_FSUB_M;
|
int CEIL_FSUB_M;
|
||||||
int CEIL_FSCAL_R;
|
int CEIL_FSCAL_R;
|
||||||
int CEIL_FMUL_R;
|
int CEIL_FMUL_R;
|
||||||
|
int CEIL_FMUL2I_R;
|
||||||
int CEIL_FDIV_M;
|
int CEIL_FDIV_M;
|
||||||
int CEIL_FSQRT_R;
|
int CEIL_FSQRT_R;
|
||||||
int CEIL_CBRANCH;
|
int CEIL_CBRANCH;
|
||||||
|
@ -183,12 +185,14 @@ struct RandomX_ConfigurationWownero : public RandomX_ConfigurationBase { RandomX
|
||||||
struct RandomX_ConfigurationLoki : public RandomX_ConfigurationBase { RandomX_ConfigurationLoki(); };
|
struct RandomX_ConfigurationLoki : public RandomX_ConfigurationBase { RandomX_ConfigurationLoki(); };
|
||||||
struct RandomX_ConfigurationArqma : public RandomX_ConfigurationBase { RandomX_ConfigurationArqma(); };
|
struct RandomX_ConfigurationArqma : public RandomX_ConfigurationBase { RandomX_ConfigurationArqma(); };
|
||||||
struct RandomX_ConfigurationSafex : public RandomX_ConfigurationBase { RandomX_ConfigurationSafex(); };
|
struct RandomX_ConfigurationSafex : public RandomX_ConfigurationBase { RandomX_ConfigurationSafex(); };
|
||||||
|
struct RandomX_ConfigurationKlaro : public RandomX_ConfigurationBase { RandomX_ConfigurationKlaro(); };
|
||||||
|
|
||||||
extern RandomX_ConfigurationMonero RandomX_MoneroConfig;
|
extern RandomX_ConfigurationMonero RandomX_MoneroConfig;
|
||||||
extern RandomX_ConfigurationWownero RandomX_WowneroConfig;
|
extern RandomX_ConfigurationWownero RandomX_WowneroConfig;
|
||||||
extern RandomX_ConfigurationLoki RandomX_LokiConfig;
|
extern RandomX_ConfigurationLoki RandomX_LokiConfig;
|
||||||
extern RandomX_ConfigurationArqma RandomX_ArqmaConfig;
|
extern RandomX_ConfigurationArqma RandomX_ArqmaConfig;
|
||||||
extern RandomX_ConfigurationSafex RandomX_SafexConfig;
|
extern RandomX_ConfigurationSafex RandomX_SafexConfig;
|
||||||
|
extern RandomX_ConfigurationKlaro RandomX_KlaroConfig;
|
||||||
|
|
||||||
extern RandomX_ConfigurationBase RandomX_CurrentConfig;
|
extern RandomX_ConfigurationBase RandomX_CurrentConfig;
|
||||||
|
|
||||||
|
|
|
@ -52,6 +52,9 @@ const RandomX_ConfigurationBase *xmrig::RxAlgo::base(Algorithm::Id algorithm)
|
||||||
case Algorithm::RX_SFX:
|
case Algorithm::RX_SFX:
|
||||||
return &RandomX_SafexConfig;
|
return &RandomX_SafexConfig;
|
||||||
|
|
||||||
|
case Algorithm::RX_KLARO:
|
||||||
|
return &RandomX_KlaroConfig;
|
||||||
|
|
||||||
default:
|
default:
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
Loading…
Add table
Add a link
Reference in a new issue