XMRig
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672f6df6c1
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Fixed Cache QoS restore on exit where it not supported.
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2021-01-24 02:23:27 +07:00 |
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XMRig
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9dae559b73
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Added RxMsr class.
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2021-01-23 23:23:39 +07:00 |
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XMRig
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b9d813c403
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Move Ryzen related fixes to RxFix class.
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2021-01-23 00:27:56 +07:00 |
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XMRig
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c48e2e6af8
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Added new class Msr.
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2021-01-22 23:50:25 +07:00 |
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XMRig
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3730bcd434
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Merge branch 'master' into feature-msr2
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2021-01-22 16:55:57 +07:00 |
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XMRig
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ea367da064
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#2043 Fix compile warning.
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2021-01-17 17:48:35 +07:00 |
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Richard Mitsuk Lavitt
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590252bd5e
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fixed grammar in a couple of awkward error messages
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2021-01-15 14:33:38 -06:00 |
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SChernykh
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f62f4e6108
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RandomX x86 JIT: remove redundant CFROUND
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2021-01-07 16:20:00 +01:00 |
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SChernykh
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ac46d6f8de
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Fix GCC warning
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2020-12-19 19:50:52 +01:00 |
|
SChernykh
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5efd00abec
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Another dataset AVX2 init speedup (+3.8% faster on Zen3)
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2020-12-19 19:46:31 +01:00 |
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SChernykh
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633aaccd9c
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Added config option for AVX2 dataset init
-1 = Auto detect
0 = Always disabled
1 = Enabled if AVX2 is supported
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2020-12-19 16:18:49 +01:00 |
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SChernykh
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410313d933
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Auto-detect the fastest code for dataset init
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2020-12-19 13:59:28 +01:00 |
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SChernykh
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515a85e66c
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Dataset initialization with AVX2 (WIP)
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2020-12-18 14:53:54 +01:00 |
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XMRig
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6b21a51a2f
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Huge pages not supported by macOS ARM.
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2020-12-16 01:59:20 +07:00 |
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XMRig
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6b331b6945
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Reduce JIT memory for ARM.
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2020-12-15 02:52:38 +07:00 |
|
SChernykh
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414588d701
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Fix alignment for Linux
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2020-12-14 18:32:25 +01:00 |
|
SChernykh
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f89f6a8abf
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Fix: secure JIT and huge pages are incompatible on Windows
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2020-12-14 18:22:58 +01:00 |
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XMRig
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87fafcf91b
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Fixed JIT on macOS.
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2020-12-12 22:40:48 +07:00 |
|
XMRig
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2966b80ba1
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Fixed macOS build.
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2020-12-12 22:15:15 +07:00 |
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XMRig
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179f09081f
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Alternative secure JIT for macOS.
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2020-12-12 21:32:36 +07:00 |
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XMRig
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775867fc3e
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Fixed secure JIT on Linux and code cleanup.
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2020-12-12 19:18:47 +07:00 |
|
XMRig
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497863441a
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Remove duplicated code.
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2020-12-12 12:39:11 +07:00 |
|
XMRig
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ec62ded279
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Added generic secure JIT support for RandomX.
|
2020-12-11 23:17:54 +07:00 |
|
SChernykh
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0da3390d09
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More static analysis fixes
|
2020-12-08 16:05:58 +01:00 |
|
SChernykh
|
cafd868773
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Fixed errors found by static analysis
|
2020-12-08 12:16:59 +01:00 |
|
XMRig
|
c8ee6f7db8
|
Move Profiler and more cleanup.
|
2020-12-04 09:23:40 +07:00 |
|
XMRig
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63bd45c397
|
Added Cvt class.
|
2020-12-02 16:31:45 +07:00 |
|
SChernykh
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d557fe7f39
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Fix RandomX init when switching to other algo and back
|
2020-11-29 22:02:48 +01:00 |
|
SChernykh
|
f16d1837f8
|
Optimized JIT compiler
More branch-free code
|
2020-11-29 14:05:50 +01:00 |
|
SChernykh
|
c10ec90b60
|
Make single thread bench cheat-resistant
Each hash is dependent on the previous hash to make multi-threaded cheating impossible.
|
2020-11-15 20:38:27 +01:00 |
|
SChernykh
|
9a1e867da2
|
Fixed MSR mod names in JSON API
|
2020-11-14 19:55:43 +01:00 |
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XMRig
|
3b6cfd9c4f
|
#1937 Print path to existing WinRing0 service without verbose option.
|
2020-11-12 23:32:49 +07:00 |
|
cohcho
|
eb36d2beef
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MemoryPool: fix alignment modification
|
2020-11-10 16:49:10 +00:00 |
|
cohcho
|
a64ff6b7c7
|
CompiledVm: define default constructor
|
2020-11-09 16:29:42 +00:00 |
|
SChernykh
|
c8c0abdb00
|
Separate MSR mod for Zen/Zen2 and Zen3
Another +0.5% speedup for Zen2
|
2020-11-08 19:40:44 +01:00 |
|
xmrig
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5df1686810
|
Merge pull request #1932 from SChernykh/dev
New MSR mod for Ryzen
|
2020-11-07 13:09:21 +07:00 |
|
SChernykh
|
1e3e8ff8ee
|
Update RxConfig.cpp
|
2020-11-06 22:59:18 +01:00 |
|
SChernykh
|
d4750239ea
|
New MSR mod for Ryzen
+3.5% on Zen2, +1-2% on Zen3
|
2020-11-06 22:56:09 +01:00 |
|
XMRig
|
51690ebad6
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#1918 Fixed check for 1GB huge pages on ARM Linux.
|
2020-11-02 21:26:35 +07:00 |
|
SChernykh
|
f1a24b7ddd
|
Fix compilation on ARMv8 with GCC 9.3.0
|
2020-11-02 13:50:10 +01:00 |
|
XMRig
|
905713f1ca
|
Merge branch 'feature-bench-submit' into dev
|
2020-10-30 23:25:09 +07:00 |
|
SChernykh
|
6b7b3511ce
|
Also fix RelWithDebIfno build in Visual Studio
|
2020-10-27 14:25:43 +01:00 |
|
SChernykh
|
50bdaba526
|
Fixed Debug build in Visual Studio
|
2020-10-27 14:08:36 +01:00 |
|
XMRig
|
4914fefb1f
|
Added "msr" field for CPU backend.
|
2020-10-25 16:36:37 +07:00 |
|
cohcho
|
99b58580e9
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MSR: supress kernel module warning
|
2020-10-23 13:09:13 +00:00 |
|
XMRig
|
87b4d97798
|
New Async wrapper.
|
2020-10-21 08:09:44 +07:00 |
|
XMRig
|
36b1523194
|
Code cleanup.
|
2020-10-16 19:35:36 +07:00 |
|
xmrig
|
9fcc542676
|
Merge pull request #1889 from cohcho/fix_uv_issue
uv: fix performance issue
|
2020-10-13 22:35:29 +07:00 |
|
SChernykh
|
4f7186cb0e
|
Added argon2/chukwav2 algorithm
New Turtlecoin algorithm. Source: https://github.com/turtlecoin/turtlecoin/blob/development/src/crypto/hash.h#L57
|
2020-10-12 08:26:57 +02:00 |
|
cohcho
|
65fa1d9bf3
|
uv: fix performance issue
unix implementation of uv_async_t has been wasting cpu cycles for nothing since 1.29.0 release
implement efficient callback scheduling for linux
|
2020-10-12 04:09:09 +00:00 |
|