fzorb/REDACTED-rig
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2 commits

Author SHA1 Message Date
SChernykh
59e8fdb9ed Added bit masks for MSR registers 2019-12-17 23:55:22 +01:00
XMRig
8bef964f68
Added support for write custom MSR. 2019-12-17 02:27:07 +07:00