- Added XLT v5/9 with autodetect(algo: "cryptonight", variant: "xtl" (autodetect), "xtlv9" (force v9))
- Added cn-lite variant UPX/uPlexa (algo: "cryptonight-lite", variant "upx")
- Added force-pow-variant parameter to force usage of the variant from the config and skip parsing of pow/variant from job/pool
* Add ASM optimizations
- Add ASM optimization for CN-FAST on INTEL
- Add ASM optimization for CNV2 on AMD Bulldozer
- Alloy is now announced as XAO
* Upgraded default configs
* Hashrate improve -> add autodetection mode for cpu-affinity
* Hashrate improve, more stable hashrates -> refactor memory allocation
* Add TubeV4 support (cn-heavy + ipbc mod + soft-aes mod)
* Update ccp-httpd lib to fix stop/freeze of cc communication on some miners
* Fix cn-heavy on arm processors
- Added shift+click function for multi row selection to Dashboard
- Added -DBUILD_STATIC=ON/OFF option to CMake configuration to create fully static builds
- Added current algo and list of supported_varaints to login message for future usage on proxy
- Added support for latest Stellite (XTL) and Alloy (XAO) variants
- Simplification of configuration, "force-pow-variant" and "cryptonight-lite-ipbc" parameters are now deprecated see [Coin Configuration](https://github.com/Bendr0id/xmrigCC/wiki/Coin-configurations) for guidance
- Fixed leaks in transport shutdown
* Debouncing of connection retry when connecting donation server fails
* When PoW variant is set on proxy, it will overrule local set PoW
* Implementation of cn_heavy algo
* Added self test for cn-heavy
* Fixed n-loop variant of powV2 and cn-heavy
* Fixed n-loop variant of powV2 and added cn-heavy for ARM
* Fixing n-loop for arm
* Limited cn-heavy to max hashfactor 3 on higher seltest fails.
* Removed a lot of casts
* Fixed algo selftest
- Fixed Bad/Invalid shares and high share transmit latency
- Fixed hugepages for some older linux versions
- Added force algo variant by xmrig-proxy 2.5.x+
- Added auto force of nicehash param by xmrig-proxy 2.5.x+
- Partial rebase of XMRig 2.5.2
This time, the performance increase is got with MSVC and GCC. On non-AES CPU, there were an useless load/store SSE2 register. The last MSVC "hack" is replaced by a portable code and he's more complete (a load is saved).
On my C2Q6600, with 3 thread, I have +16% with MSVC2015 and +20% with GCC 7.3, compared to official 2.4.4 version.
