BenDroid
35fc62677f
Changed download urls
2018-03-01 21:20:02 +01:00
BenDroid
8d09bc9800
windows buildserver fixes
2018-03-01 21:10:29 +01:00
BenDroid
7f36b9eb3e
More buildserver fixes
2018-03-01 21:05:25 +01:00
BenDroid
8bbd30695c
Changes in build config
2018-03-01 20:57:51 +01:00
BenDroid
e9b2a73635
Fixing mvsc build server breaks
2018-03-01 20:23:13 +01:00
BenDroid
e3d647859c
Added new dependencie package to appveyor
2018-03-01 20:04:19 +01:00
Ben Gräf
19a68424c2
Merge remote-tracking branch 'origin/dev_tls' into dev_tls
2018-03-01 17:44:27 +01:00
Ben Gräf
9d0f570577
Fixed TLS build on Windows GCC/MVSC
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Cleanup TLS compile
2018-03-01 17:44:15 +01:00
Unknown
fa0d1e2d0e
Made executable names of miner and daemon settable via CMake parameters.
2018-03-01 13:10:55 +01:00
Ben Gräf
67220c8d3d
Added new features to Readme
2018-02-26 21:35:50 +01:00
Ben Gräf
48493bbbb2
Update Options.cpp
2018-02-26 11:44:37 +01:00
Ben Gräf
c3aa7b446b
Cleanup
2018-02-26 09:19:46 +01:00
BenDroid
1343d89d59
Merged branch wip_tls_stratum_2nd_approach into dev_tls
2018-02-25 23:33:41 +01:00
BenDroid
69afccf762
Cleanup and added integrated tls config params parsing
2018-02-25 23:32:51 +01:00
BenDroid
b26c1d637a
Added clibs-net and clibs-buffer to 3rdparty
2018-02-25 22:10:49 +01:00
BenDroid
6b13f2ad88
Added SSL/TLS support to stratum communication
2018-02-25 22:06:40 +01:00
Ben Gräf
c5fa48215b
Merge remote-tracking branch 'origin/master' into dev_tls
2018-02-22 08:36:12 +01:00
BenDroid
9e37fa98fd
Manual merged #43 Mac OS Compilation fixes
2018-02-21 23:17:11 +01:00
BenDroid
97df127e81
Fixed hugepages on MacOSx
2018-02-21 23:09:29 +01:00
xmrig
79345119c6
Update CHANGELOG.md
2018-02-19 15:58:44 +07:00
XMRig
9af8ceb063
v2.4.5 RC
2018-02-19 04:31:50 +07:00
xmrig
f5a0429f0d
Update README.md
2018-02-19 04:17:50 +07:00
xmrig
cc22c9d61c
Update README.md
2018-02-18 05:49:37 +07:00
xmrig
45f5afd2b7
Merge pull request #379 from DeadManWalkingTO/master
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Update README.md
2018-02-18 05:48:09 +07:00
xmrig
c9acc2912e
Update CHANGELOG.md
2018-02-18 05:32:36 +07:00
xmrig
f0604d1e97
Update README.md
2018-02-18 05:06:10 +07:00
BenDroid
e082a3d093
Added tls flag to Url
2018-02-09 20:16:07 +01:00
BenDroid
7f9e86a627
Fixed behavior for non-tls mode
2018-02-09 20:15:11 +01:00
XMRig
531c657b64
Merge branch 'master' of github.com:xmrig/xmrig
2018-02-08 17:35:20 +07:00
XMRig
c50ccd4e06
Merge branch 'Foudge-master'
2018-02-08 17:34:33 +07:00
XMRig
184f79ad3f
Fix code style, replace tabs to space #2 .
2018-02-08 17:21:12 +07:00
XMRig
e78e810cfe
Fix code style, replace tabs to space.
2018-02-08 17:02:32 +07:00
XMRig
c804ef1888
Merge branch 'master' of https://github.com/Foudge/xmrig into Foudge-master
2018-02-08 16:56:20 +07:00
BenDroid
576d5f06ae
Merged branch master into dev_tls
2018-02-06 21:44:10 +01:00
BenDroid
1330ffae0b
Fixed Uptime column in Dashboard
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Implemented HTTPS for miner -> server and server -> dashboard
2018-02-06 21:43:53 +01:00
BenDroid
054b302ab5
Added miner uptime to dashboard
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WIP SSL/TLS for CC communication and Dashboard
2018-02-05 22:53:38 +01:00
Foudge
037abd7037
Correct L2 cache size calculation for Intel Core 2 family
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This is a workaround for total L2 cache size calculation of Intel Core Solo, Core Duo, Core 2 Duo, Core 2 Quad and their Xeon homologue. These processors have L2 cache shared by 2 cores.
There is maybe more CPU with L2 shared cache, but I am sure that these models are concerned and they are not so numerous.
A better way would be to modify libcpuid to implement L2 cache counting.
2018-02-03 16:31:13 +01:00
DeadManWalking
75f462f0e1
Update README.md
2018-02-02 00:58:11 +02:00
DeadManWalking
9f92449e15
Update README.md
2018-02-02 00:54:58 +02:00
DeadManWalking
a917590862
Update README.md
2018-02-02 00:14:39 +02:00
DeadManWalking
41b92740ea
Merge pull request #1 from xmrig/master
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!
2018-02-01 23:02:32 +02:00
Ben Gräf
0b12e50ac3
Update README.md
2018-01-30 20:45:54 +01:00
Foudge
d2964576c7
Compilation error under FreeBSD
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ULONG is not recognized under this OS, so replaced it with more portable definition.
2018-01-28 18:13:00 +01:00
Foudge
9a28ad590c
up to 20% perf increase with Cryptonight with non-AES CPU
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This time, the performance increase is got with MSVC and GCC. On non-AES CPU, there were an useless load/store SSE2 register. The last MSVC "hack" is replaced by a portable code and he's more complete (a load is saved).
On my C2Q6600, with 3 thread, I have +16% with MSVC2015 and +20% with GCC 7.3, compared to official 2.4.4 version.
2018-01-28 12:58:19 +01:00
Foudge
15fe6ce23f
Remove compilation warnings under MSVC
2018-01-27 11:42:22 +01:00
xmrig
17f90de677
Merge pull request #353 from Foudge/master
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up to 15% boost on CryptoNight algo with non-AES CPU
2018-01-26 00:53:22 +07:00
Ben Gräf
dd1f131938
Update README.md
2018-01-24 21:44:40 +01:00
Ben Gräf
a63f2ee924
Update README.md
2018-01-24 21:40:44 +01:00
BenDroid
b47e5623a4
Alignment
2018-01-24 21:32:38 +01:00
BenDroid
9f82f98118
Merged branch master into master
2018-01-24 21:31:41 +01:00
