83 lines
2.8 KiB
C++
83 lines
2.8 KiB
C++
/* XMRig
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* Copyright 2010 Jeff Garzik <jgarzik@pobox.com>
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* Copyright 2012-2014 pooler <pooler@litecoinpool.org>
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* Copyright 2014 Lucas Jones <https://github.com/lucasjones>
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* Copyright 2014-2016 Wolf9466 <https://github.com/OhGodAPet>
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* Copyright 2016 Jay D Dee <jayddee246@gmail.com>
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* Copyright 2016-2017 XMRig <support@xmrig.com>
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* Copyright 2018 Sebastian Stolzenberg <https://github.com/sebastianstolzenberg>
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*
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <cmath>
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#include <cstring>
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#include <algorithm>
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#include <memory>
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#include <libcpuid.h>
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#include <iostream>
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#include "Cpu.h"
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#include "CpuImpl.h"
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void CpuImpl::initCommon()
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{
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struct cpu_raw_data_t raw = { 0 };
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struct cpu_id_t data = { 0 };
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cpuid_get_raw_data(&raw);
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cpu_identify(&raw, &data);
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strncpy(m_brand, data.brand_str, sizeof(m_brand) - 1);
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m_totalThreads = data.total_logical_cpus;
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m_sockets = m_totalThreads / data.num_logical_cpus;
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if (m_sockets == 0) {
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m_sockets = 1;
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}
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m_totalCores = data.num_cores * m_sockets;
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m_l3_cache = data.l3_cache > 0 ? data.l3_cache * m_sockets : 0;
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// Workaround for AMD CPUs https://github.com/anrieff/libcpuid/issues/97
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if (data.vendor == VENDOR_AMD && data.ext_family >= 0x15 && data.ext_family < 0x17) {
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m_l2_cache = data.l2_cache * (m_totalCores / 2) * m_sockets;
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m_l2_exclusive = true;
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}
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// Workaround for Intel Pentium Dual-Core, Core Duo, Core 2 Duo, Core 2 Quad and their Xeon homologue
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// These processors have L2 cache shared by 2 cores.
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else if (data.vendor == VENDOR_INTEL && data.ext_family == 0x06 && (data.ext_model == 0x0E || data.ext_model == 0x0F || data.ext_model == 0x17)) {
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int l2_count_per_socket = m_totalCores > 1 ? m_totalCores / 2 : 1;
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m_l2_cache = data.l2_cache > 0 ? data.l2_cache * l2_count_per_socket * m_sockets : 0;
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}
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else{
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m_l2_cache = data.l2_cache > 0 ? data.l2_cache * m_totalCores * m_sockets : 0;
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}
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# if defined(__x86_64__) || defined(_M_AMD64)
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m_flags |= Cpu::X86_64;
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# endif
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if (data.flags[CPU_FEATURE_AES]) {
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m_flags |= Cpu::AES;
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}
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if (data.flags[CPU_FEATURE_BMI2]) {
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m_flags |= Cpu::BMI2;
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}
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}
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