From 1529bb48c87bbe3af1d9aeeb2bd10cfe396dcd13 Mon Sep 17 00:00:00 2001
From: Ryan Houdek <Sonicadvance1@Gmail.com>
Date: Mon, 16 Sep 2013 15:44:41 +0000
Subject: [PATCH] [ARM] Flush the fpr cache between every instruction. Do this
 until I figure out what is destroying the FPR register states.

---
 Source/Core/Core/Src/PowerPC/JitArm32/Jit.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/Jit.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/Jit.cpp
index 8b11840682..c7cdb81d21 100644
--- a/Source/Core/Core/Src/PowerPC/JitArm32/Jit.cpp
+++ b/Source/Core/Core/Src/PowerPC/JitArm32/Jit.cpp
@@ -483,6 +483,7 @@ const u8* JitArm::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBlo
 					BKPT(0x7777);
 				}
 				JitArmTables::CompileInstruction(ops[i]);
+				fpr.Flush();
 				if (js.memcheck && (opinfo->flags & FL_LOADSTORE))
 				{
 					// Don't do this yet