From 246adf0d6dbefc329f1347000be4b9ea3aa3447e Mon Sep 17 00:00:00 2001 From: Sintendo Date: Wed, 24 Mar 2021 22:40:35 +0100 Subject: [PATCH] Jit64: divwx - Eliminate MOV for division by 2 When destination and input registers match, a redundant MOV instruction can be eliminated. Before: 8B C7 mov eax,edi 8B F8 mov edi,eax C1 EF 1F shr edi,1Fh 03 F8 add edi,eax D1 FF sar edi,1 After: 8B C7 mov eax,edi C1 EF 1F shr edi,1Fh 03 F8 add edi,eax D1 FF sar edi,1 --- Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp b/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp index d2294ba313..b77914ef99 100644 --- a/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp +++ b/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp @@ -1464,12 +1464,21 @@ void Jit64::divwx(UGeckoInstruction inst) else if (divisor == 2 || divisor == -2) { X64Reg tmp = RSCRATCH; - if (Ra.IsSimpleReg() && Ra.GetSimpleReg() != Rd) - tmp = Ra.GetSimpleReg(); - else + if (!Ra.IsSimpleReg()) + { MOV(32, R(tmp), Ra); + MOV(32, Rd, R(tmp)); + } + else if (d == a) + { + MOV(32, R(tmp), Ra); + } + else + { + MOV(32, Rd, Ra); + tmp = Ra.GetSimpleReg(); + } - MOV(32, Rd, R(tmp)); SHR(32, Rd, Imm8(31)); ADD(32, Rd, R(tmp)); SAR(32, Rd, Imm8(1));