From 55b9ce9b5b817d3aff6a55cf4a1a55aab0f91046 Mon Sep 17 00:00:00 2001
From: degasus <wickmarkus@web.de>
Date: Mon, 29 Feb 2016 00:20:39 +0100
Subject: [PATCH] JitArm64: Store memory pointer once, not per block.

---
 Source/Core/Core/PowerPC/JitArm64/Jit.cpp             | 5 +----
 Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.h | 1 +
 Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp          | 8 +++++---
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/Source/Core/Core/PowerPC/JitArm64/Jit.cpp b/Source/Core/Core/PowerPC/JitArm64/Jit.cpp
index 07821bd0bf..6494863349 100644
--- a/Source/Core/Core/PowerPC/JitArm64/Jit.cpp
+++ b/Source/Core/Core/PowerPC/JitArm64/Jit.cpp
@@ -205,6 +205,7 @@ void JitArm64::WriteExit(u32 destination)
 
 	b->linkData.push_back(linkData);
 }
+
 void JitArm64::WriteExceptionExit(ARM64Reg dest)
 {
 	Cleanup();
@@ -464,10 +465,6 @@ const u8* JitArm64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitB
 	gpr.Start(js.gpa);
 	fpr.Start(js.fpa);
 
-	// Setup memory base register
-	u8* base = UReg_MSR(MSR).DR ? Memory::logical_base : Memory::physical_base;
-	MOVI2R(X28, (u64)base);
-
 	if (!SConfig::GetInstance().bEnableDebugging)
 		js.downcountAmount += PatchEngine::GetSpeedhackCycles(em_address);
 
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.h b/Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.h
index 6616e4b6fb..e5b35a3036 100644
--- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.h
+++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.h
@@ -13,6 +13,7 @@
 
 // Dedicated host registers
 // X29 = ppcState pointer
+// X28 = memory base register
 using namespace Arm64Gen;
 
 enum RegType
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp b/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp
index fd99cae155..d0b00c53cd 100644
--- a/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp
+++ b/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp
@@ -26,6 +26,8 @@ void JitArm64AsmRoutineManager::Generate()
 	ABI_PushRegisters(regs_to_save);
 
 	MOVI2R(X29, (u64)&PowerPC::ppcState);
+	MOVI2R(X28, (u64)Memory::logical_base);
+
 	FixupBranch to_dispatcher = B();
 
 	// If we align the dispatcher to a page then we can load its location with one ADRP instruction
@@ -44,11 +46,11 @@ void JitArm64AsmRoutineManager::Generate()
 
 		// This block of code gets the address of the compiled block of code
 		// It runs though to the compiling portion if it isn't found
-		LDR(INDEX_UNSIGNED, W28, X29, PPCSTATE_OFF(pc)); // Load the current PC into W28
-		BFM(W28, WSP, 3, 2); // Wipe the top 3 bits. Same as PC & JIT_ICACHE_MASK
+		LDR(INDEX_UNSIGNED, W26, X29, PPCSTATE_OFF(pc)); // Load the current PC into W26
+		BFM(W26, WSP, 3, 2); // Wipe the top 3 bits. Same as PC & JIT_ICACHE_MASK
 
 		MOVI2R(X27, (u64)jit->GetBlockCache()->iCache.data());
-		LDR(W27, X27, X28);
+		LDR(W27, X27, X26);
 
 		FixupBranch JitBlock = TBNZ(W27, 7); // Test the 7th bit
 			// Success, it is our Jitblock.