diff --git a/Source/Core/Common/ArmEmitter.cpp b/Source/Core/Common/ArmEmitter.cpp
index ded0944e57..ccd05d4c45 100644
--- a/Source/Core/Common/ArmEmitter.cpp
+++ b/Source/Core/Common/ArmEmitter.cpp
@@ -401,7 +401,7 @@ void ARMXEmitter::SetJumpTarget(FixupBranch const &branch)
 	_dbg_assert_msg_(DYNA_REC, distance > -0x2000000 && distance <= 0x2000000,
 	                 "SetJumpTarget out of range (%p calls %p)", code, branch.ptr);
 	u32 instr = (u32)(branch.condition | ((distance >> 2) & 0x00FFFFFF));
-	instr |= branch.type ? /* B */ 0x0A000000 : /* BL */ 0x0B000000;
+	instr |= (0 == branch.type) ? /* B */ 0x0A000000 : /* BL */ 0x0B000000;
 	*(u32*)branch.ptr = instr;
 }
 void ARMXEmitter::B(const void *fnptr)
diff --git a/Source/Core/Core/PowerPC/JitArm32/JitArm_LoadStore.cpp b/Source/Core/Core/PowerPC/JitArm32/JitArm_LoadStore.cpp
index c660d0387a..16cd8fb7b8 100644
--- a/Source/Core/Core/PowerPC/JitArm32/JitArm_LoadStore.cpp
+++ b/Source/Core/Core/PowerPC/JitArm32/JitArm_LoadStore.cpp
@@ -19,7 +19,7 @@
 void JitArm::UnsafeStoreFromReg(ARMReg dest, ARMReg value, int accessSize, s32 offset)
 {
 	// All this gets replaced on backpatch
-	Operand2 mask(3, 1); // ~(Memory::MEMVIEW32_MASK)
+	Operand2 mask(2, 1); // ~(Memory::MEMVIEW32_MASK)
 	BIC(dest, dest, mask); // 1
 	MOVI2R(R14, (u32)Memory::base, false); // 2-3
 	ADD(dest, dest, R14); // 4
@@ -212,7 +212,7 @@ void JitArm::UnsafeLoadToReg(ARMReg dest, ARMReg addr, int accessSize, s32 offse
 	ADD(addr, addr, rA); // - 1
 
 	// All this gets replaced on backpatch
-	Operand2 mask(3, 1); // ~(Memory::MEMVIEW32_MASK)
+	Operand2 mask(2, 1); // ~(Memory::MEMVIEW32_MASK)
 	BIC(addr, addr, mask); // 1
 	MOVI2R(rA, (u32)Memory::base, false); // 2-3
 	ADD(addr, addr, rA); // 4
@@ -461,7 +461,7 @@ void JitArm::lmw(UGeckoInstruction inst)
 	MOVI2R(rA, inst.SIMM_16);
 	if (a)
 		ADD(rA, rA, gpr.R(a));
-	Operand2 mask(3, 1); // ~(Memory::MEMVIEW32_MASK)
+	Operand2 mask(2, 1); // ~(Memory::MEMVIEW32_MASK)
 	BIC(rA, rA, mask); // 3
 	MOVI2R(rB, (u32)Memory::base, false); // 4-5
 	ADD(rA, rA, rB); // 6
@@ -493,7 +493,7 @@ void JitArm::stmw(UGeckoInstruction inst)
 	MOVI2R(rA, inst.SIMM_16);
 	if (a)
 		ADD(rA, rA, gpr.R(a));
-	Operand2 mask(3, 1); // ~(Memory::MEMVIEW32_MASK)
+	Operand2 mask(2, 1); // ~(Memory::MEMVIEW32_MASK)
 	BIC(rA, rA, mask); // 3
 	MOVI2R(rB, (u32)Memory::base, false); // 4-5
 	ADD(rA, rA, rB); // 6
diff --git a/Source/Core/Core/PowerPC/JitArm32/JitArm_LoadStoreFloating.cpp b/Source/Core/Core/PowerPC/JitArm32/JitArm_LoadStoreFloating.cpp
index cc1e0b4e4a..3a78c45b29 100644
--- a/Source/Core/Core/PowerPC/JitArm32/JitArm_LoadStoreFloating.cpp
+++ b/Source/Core/Core/PowerPC/JitArm32/JitArm_LoadStoreFloating.cpp
@@ -129,7 +129,7 @@ void JitArm::lfXX(UGeckoInstruction inst)
 
 	if (Core::g_CoreStartupParameter.bFastmem)
 	{
-		Operand2 mask(3, 1); // ~(Memory::MEMVIEW32_MASK)
+		Operand2 mask(2, 1); // ~(Memory::MEMVIEW32_MASK)
 		BIC(rB, rB, mask); // 1
 		MOVI2R(rA, (u32)Memory::base, false); // 2-3
 		ADD(rB, rB, rA); // 4
@@ -291,7 +291,7 @@ void JitArm::stfXX(UGeckoInstruction inst)
 	}
 	if (Core::g_CoreStartupParameter.bFastmem)
 	{
-		Operand2 mask(3, 1); // ~(Memory::MEMVIEW32_MASK)
+		Operand2 mask(2, 1); // ~(Memory::MEMVIEW32_MASK)
 		BIC(rB, rB, mask); // 1
 		MOVI2R(rA, (u32)Memory::base, false); // 2-3
 		ADD(rB, rB, rA); // 4