Sintendo 47e16133e5 Jit64: divwx - Eliminate XOR for constant dividend ... We normally check for division by zero to know if we should set the destination register to zero with a XOR. However, when the divisor and destination registers are the same the explicit zeroing can be omitted. In addition, some of the surrounding branching can be simplified as well. Before: 45 85 FF test r15d,r15d 75 05 jne normal_path 45 33 FF xor r15d,r15d EB 0C jmp done normal_path: B8 5A 00 00 00 mov eax,5Ah 99 cdq 41 F7 FF idiv eax,r15d 44 8B F8 mov r15d,eax done: After: 45 85 FF test r15d,r15d 74 0C je done B8 5A 00 00 00 mov eax,5Ah 99 cdq 41 F7 FF idiv eax,r15d 44 8B F8 mov r15d,eax done:		2021-04-24 21:32:21 +02:00
..
Android	Merge pull request #9653 from JosJuice/android-import-nand	2021-04-19 21:57:40 +02:00
Core	Jit64: divwx - Eliminate XOR for constant dividend	2021-04-24 21:32:21 +02:00
DSPSpy	DSPSpy: sync Makefile with current devkitPro template	2020-06-08 04:21:41 +01:00
DSPTool	Set console's default language/country/region based on computer settings	2021-03-27 10:05:26 +01:00
PCH	Fix PCH when building with CMake + Ninja + MSVC on Windows	2021-04-17 17:48:47 +02:00
UnitTests	UnitTests: Use MathUtil::SaturatingCast to avoid UB	2021-04-06 23:27:23 +02:00
VSProps	msbuild: re-enable HAS_OPENGL and HAS_VULKAN	2021-01-27 19:10:53 -08:00
.clang-format
CMakeLists.txt	CMake: Build with -std:c++latest for MSVC	2021-03-03 23:44:35 +01:00
dolphin-emu.sln	msbuild: bundle all dolphin "core" code into single library	2021-01-27 14:29:49 -08:00