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Tweaked autoconfig for AMD CPUs with < 2 MB L3 cache per thread

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SChernykh 2025-06-11 18:34:50 +02:00
parent d24e13e605
commit e4c30eb0dd
1 changed files with 2 additions and 1 deletions
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src/backend/cpu/platform/HwlocCpuInfo.cpp
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@ -322,7 +322,8 @@ void xmrig::HwlocCpuInfo::processTopLevelCache(hwloc_obj_t cache, const Algorith
if (L3_exclusive) { if (L3_exclusive) {
if (vendor() == VENDOR_AMD) { if (vendor() == VENDOR_AMD) {
extra += std::min<size_t>(l2->attr->cache.size, scratchpad); // For some reason, AMD CPUs can use only half of the exclusive L2/L3 cache combo efficiently
extra += std::min<size_t>(l2->attr->cache.size / 2, scratchpad);
} }
else if (l2->attr->cache.size >= scratchpad) { else if (l2->attr->cache.size >= scratchpad) {
extra += scratchpad; extra += scratchpad;